A feature of the system of the invention is that each CPU in the system is capable of accessing two buses, one directly and the other indirectly. Then, by virtue of a "reach-through" operation, each CPU is capable of accessing any other bus within the system. For most operations, each CPU operates independently and autonomously in the system. However, when required, any CPU can communicate with any other CPU within the system in a rapid and efficient manner.
The prior art communication systems from one CPU to another do not usually involve the temporary takeover of the bus of one CPU by another CPU. Instead, one CPU derives data from its memory and places the data in a communication channel, and a second CPU takes the data from the communication channel and places it in its memory. This involves the overhead of two operating CPU's, and additional overhead involving handshaking and status passing operations.
In the system of the present invention, on the other hand, only one operating CPU is involved during the communication phase, and that CPU is capable of withdrawing data from the memory of another CPU and of storing the data in its own memory by taking over the bus of the other CPU.
For example, the situation may be considered in which a first CPU is required to transfer data to a second CPU. With the bus takeover feature of the system of the present invention, a master CPU is caused to take over a sub-system CPU, rendering the sub-system CPU inactive, and setting up a data transfer from the memory of the sub-system CPU to the memory of the master CPU. The master CPU may proceed with other operations while the transfer is taking place. After the transfer has been completed, the master CPU releases the sub-system CPU allowing it again to operate independently of the master CPU. The total elapsed time of the takeover of the sub-system CPU, the transfer of data, and the release of the sub-system CPU, is less than that required in the prior art systems by a factor of 2:10, or more.
The bus takeover system of the invention may be used, for example, as a general purpose computer system composed of several CPU sub-systems. One master CPU sub-system assigns tasks to each of the other CPU sub-systems. Each CPU sub-system may be of the general purpose type, and they may all be identical; or each CPU sub-system may be specialized. For example, one CPU sub-system may be in charge of printers and terminals, and another CPU subsystem may be in charge of mass storage, and so on.
In the system describe in the preceding paragraph, the master CPU sub-system takes over the bus of another CPU sub-system only long enough to transfer data between the sub-systems, either to initialize a task, or to withdraw the results. At all other times each CPU sub-system operates independently of all others.
Another field of use for the bus takeover system of the invention is in conjunction with disk-drive test equipment of the type in which many CPU sub-systems are involved in testing different groups of disk drives. In such a system, the master CPU sub-system takes care of operator communication and supervision of the various CPU sub-systems. Each CPU sub-system is independent of all other sub-systems during its test sequences. However, when the master is conditioned to redirect the sequence, or to withdraw test result data, the master takes over each sub-system only long enough to transfer data to or from the particular sub-system.